In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (μP) chips, and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices. An SOC device integrates into a single chip many of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). SOC devices greatly reduce the size, cost, and power consumption of the system.
SOC data processors are characterized by a very high degree of integration on a single integrated circuit (IC) chip. Many of the peripheral components now integrated onto the same IC chip as a processor core would have been implemented as separate IC chips in a previous generation of processors. Advantageously, this decreases the amount of board space required, reduces the effects of noise, allows for low-voltage operations, and, in many cases, reduces the pin count of the SOC device.
SOC devices comprise a plurality of individual modules that communicate with each other by sending data over one or more internal data buses. For convenience, a module that sends data over a data bus may be referred to as a “master unit” and a module that receives data over a data bus may be referred to as a “slave unit.” Data transmissions over a data bus in a SOC processor may comprise a plurality of individual packets of data. An individual packet of data may comprise, for example, sixty four (64) bits of data. A data transmission of a single packet of data over a data bus may be referred to as a “data transaction.”
There are generally two types of data buses available for use in a SOC device. The first type of data bus is referred to as an “in order” data bus. The second type of data bus is referred to as an “out of order” data bus. When a master unit sends a plurality of data transactions over an “in order” data bus, the slave unit receives the data transactions and executes the data transactions exactly in the order that they are received by the slave unit. That is why the data bus is referred to as an “in order” data bus. The data transactions are executed in order of their arrival in the slave unit.
On the other hand, when a master unit sends a plurality of data transactions over an “out of order” data bus, the slave unit receives the data transactions in the order in which they were sent by the master unit, but the slave unit does not necessarily execute the data transactions in the order in which they were received.
When the slave unit receives data transactions on an “in order” bus, the slave unit cannot reorder the execution of the data transactions to optimize the utilization of slave unit resources (e.g., dynamic random access memory). When the slave unit receives data transactions on an “out of order” bus, however, the slave unit can reorder the execution of the data transactions to optimize the utilization of slave unit resources. But the use of an “out of order” bus increases latencies for the master unit and requires the master unit to provide reordering buffering for the data transactions. In some cases the order in which the data transactions are to be executed by the slave unit is relevant. In those cases the use of an “out of order” bus prevents the master unit from controlling the ordering of the data transactions.
Therefore, there is a need in the art for an apparatus and method for sending “in order” data transactions and “out of order” data transactions on the same data bus. In particular, there is a need in the art for improved system-on-a-chip (SOC) devices and other large-scale integrated circuits in which a master unit is capable of specifying which data transactions are to be handled “in order” with respect to other data transactions and which data transactions are to be handled “out of order” with respect to other data transactions.